5 patents selected (of 366 matches).PatentWebの連続出力 H12.12.13
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dvd and encod* ←・・・検索式
5 patents selected (of 366 matches) ←・・・366件該当した。
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Search scope: US ; Full patent spec.
Years: 2000
Text: dvd and encod*
5 patents selected (of 366 matches).
Table of Contents
1. US6148428 H03M 20001114 Calimetrics, Inc.
Method and apparatus for modulation encoding data for storage on a multi-level optical recording medium
2. US6148387 G06F 20001114 Phoenix Technologies, Ltd.
System and method for securely utilizing basic input and output system (BIOS) services
3. US6148316 G06F 20001114 Mentor Graphics Corporation
Floating point unit equipped also to perform integer addition as well as floating point to integer conversion
4. US6148140 H04N 20001114 Matsushita Electric Industrial Co., Ltd.
Video data editing apparatus, optical disc for use as a recording medium of a video data editing apparatus, and computer readable recording medium storing an editing program
5. US6148135 G03B 20001114 Mitsubishi Denki Kabushiki Kaisha
Video and audio reproducing device and video decoding device
Record 1
Abstract: A system and method are disclosed for modulation encoding data for storage or transmission on a multilevel medium. The method includes encoding a first portion of data using a first tier modulation code. The first tier modulation code maps a first portion of the data onto a first set of symbols. A second portion of data is encoded using a second tier modulation code. The second tier modulation maps the second portion of the data onto a second set of symbols. The second tier modulation code has error correcting characteristics. A third set of symbols is determined based on the first set of symbols and the second set of symbols. The third set of symbols is suitable to determine nominal read signal levels from a multilevel medium. Improved error characteristics are realized for encoding data for storage or transmission on a multilevel medium.
US.Class: 714752 370204
Int'l Class: H03M01300
US Patents Cited: 3706842 3849595 4217467 4860312 5267248 5448592 5459709 5537382 5654986 5751773 5818806 5909449 6034996
Other References: Kasami, et al. (On Multilevel Block Modulation Codes, IEEE, 1991). T. Kasami, T. Takata and T. Fujiwara, On Multilevel Block Modulation Codes, Jul. 4, 1991, IEEE Transactions on Information Theory, vol. 37, No. 4. H. Imai and S. Hirakawa, A New Multilevel Coding Method Using Error-Correcting Codes, Apr. 12, 1976, IEEE Transactions on Information Theory, vol. IT-23, No. 3.
Agent(s): Ritter, Van Pelt � Lamarre, Guy
Record 2
Abstract: In accordance with one aspect of the current invention, the system comprises a memory for storing instruction sequences by which the processor-based system is processed, where the memory includes a physical memory and a virtual memory. The system also comprises a processor for executing the stored instruction sequences. The stored instruction sequences include process acts to cause the processor to: map a plurality of predetermined instruction sequences from the physical memory to the virtual memory, determine an offset to one of the plurality of predetermined instruction sequences in the virtual memory, receive an instruction to execute the one of the plurality of predetermined instruction sequences, transfer control to the one of the plurality of predetermined instruction sequences, and process the one of the plurality of predetermined instruction sequences from the virtual memory. In accordance with another aspect of the present invention, the system includes an access driver to generate a service request to utilize BIOS services such that the service request contains a service request signature created using a private key in a cryptographic key pair. The system also includes an interface to verify the service request signature using a public key in the cryptographic key pair to ensure integrity of the service request.
US.Class: 711203 711006 711173 711202 711204 711205 395651 395652
Int'l Class: G06F00900
US Patents Cited: 4563737 4742447 4868738 4926322 4928237 5133058 5193161 5212633 5255379 5301287 5361340 5388242 5459867 5459869 5675762 5696970 5758124
Other References: Interface Synthesis for Embedded Applications in a CoDesign Environment, Basu et al. IEEE 1997, p. 85-90.
Related Data: 947990 19971009
Agent(s): Irell � Nguyen, Than
Record 3
Abstract: An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU includes a shifter, a bypass datapath, and a bypass multiplexer. The shifter receives an operand input and a control input, and shifts the operand input in accordance with the control input. The bypass datapath bypasses the operand input around the shifter. The bypass multiplexer is coupled to the shifter and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable an integer addition if the operand is an integer operand, and selects the shifter to enable a floating point addition or floating point to integer conversion if the operand is a floating point operand. In an alternate embodiment, the FPU includes an alignment unit, an arithmetic logic unit (ALU), a bypass datapath, and a bypass multiplexer. The alignment unit receives a first input and a second input, and aligns them. The ALU is coupled to the alignment unit and receives and adds the aligned first and second inputs. he bypass datapath bypasses a predetermined one of the aligned inputs around the ALU. The bypass multiplexer is coupled with the ALU and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable a floating point to integer conversion if the other input is an integer conversion factor, and selects the ALU to enable an integer or floating point addition if the other input is an integer or floating point number.
US.Class: 708505 708495 708204
Int'l Class: G06F00742 G06F00738 G06F00700
US Patents Cited: 5561810 5677861 5901076 5923575
Agent(s): Columbia IP Law Group, LLC
Examiner(s): Mai, Tan V.;
Record 4
Abstract: One or more video objects are recorded on an optical disc. When a user indicates a linking edit that links sections of the video objects, video object units (VOBUs) that include picture data at the end of a former section and VOBUs that include picture data at the start of a latter section are read from the optical disc and the audio packs and video packs are separated from these read VOBS. Next, the video packs are re-encoded and some of the audio packs that were originally in the former section are multiplexed into the latter section. The result of the multiplexing is then recorded onto the optical disc.
US.Class: 386105 386126
Int'l Class: H04N005928
Priority: JP 9-251995 19970917
US Patents Cited: 5559562 5802240 5854873 5905845 5923869 5937138
Foreign References: EP0681292A2 EP0724264A2 EP0734159A1 EP0801392A2 JP09163305A WO9703443 WO9706531 WO9713363 WO9746007
Other References: R. Hedtke et al., "Schnittbearbeitung von MPEG-2-codierten Videosequenzen", Fernseh-Und Kino-Technik, vol. 50, No. 7, Jul. 1, 1996, pp. 367-373. Y. Uesaka, "DVD Authoring System", National Technical Report, vol. 42, No. 5, Oct. 1996, pp. 90-96. S. W. Ryu et al., "A Hierarchical Layered Model for DVD Authoring System", IEEE Transactions on Consumer Electronics, vol. 42, No. 3, Aug. 1996, pp. 814-819.
Agent(s): Wenderoth, Lind & Ponack, L.L.P.
Examiner(s): Nguyen, Huy;
Record 5
Abstract: The video and audio synchronization controller sets a system clock reference (SCR) included in the frame header portion of the coded video and audio data into a system time counter to set a timing of a system time clock (STC), immediately after a video and audio reproducing device has been powered on. The video and audio reproducing device decodes and displays a first arriving video data synchronous with a display system frame pulse, which is the closest to the value of a video time stamp included in a frame header of the first video frame on the time axis of the set STC. The video and audio synchronization controller sets again the value of the time stamp included in the first video frame to the system time counter to update the STC. The video and audio reproducing device outputs the video data for the second and subsequent video frames and all the audio data synchronous with the updated STC by outputting the video and audio data when the time indicated by the video and audio time stamps arrives on the time axis of the updated STC.
US.Class: 386012 386098 348423 348462 348512
Int'l Class: G03B03100
Priority: JP 8-12769 19960129
US Patents Cited: 4832481 5287182 5325125 5481543 5502573 5535137 5537148 5598352 5808722 5815634 5913031
Other References: "Coding Of Moving Pictures And Associated Audio", ISO/IECJTC1/SC29/WG11 N0802, Nov. 9, 1994. "Coding Of Moving Pictures And Associated Audio", ISO/IECJTC1/SC29/WG11 N0801, Nov. 13, 1994.
Related Data: 5808722 XXXXXX 655887 19960531
Agent(s): Leydig, Voit � Pham, Thanh I.
